| PART |
Description |
Maker |
| SY100EP58VZI SY100EP58VZITR |
3.3V/5V 3GHz PECL/ECL 2:1 MULTIPLEXER 100E SERIES, 2 LINE TO 1 LINE MULTIPLEXER, COMPLEMENTARY OUTPUT, PDSO8
|
Micrel Semiconductor, Inc.
|
| MC100LVE222 MC100LVE222FAR2 ON0511 MC100LVE222FA |
0.345A, 2.7-5.5V Quad (2In/ 4Out) Hi-Side MOSFET, Fault Report, Act-Low Enable 16-SOIC 0 to 85
Low Voltage 1:15 Differential ±1±2 ECL/PECL Clock Driver
From old datasheet system
MARKING DIAGRAM
Low Voltage 1:15 Differential 12 ECL/PECL Clock Driver
Low Voltage 1:15 Differential ÷1÷2 ECL/PECL Clock Driver
|
ONSEMI[ON Semiconductor]
|
| MC100LVEL91 MC100LVEL91DW MC100EL91 MC100EL91DW ON |
From old datasheet system
Triple PECL to ECL T ranslator
Triple PECL to ECL Translator
|
ONSEMI[ON Semiconductor]
Motorola, Inc
|
| AZ100E116FN AZ10E116 |
ECL/PECL Quint Differential Line Receiver ECL / PECL的昆特差分线路接收器
|
Arizona Microtek, Inc.
|
| AZHEL11 AZM100EL11 AZ100EL11D |
ECL/PECL 1:2 Differential Fanout Buffer ECL / PECL的差:2扇出缓冲
|
Electronic Theatre Controls, Inc.
ETC
|
| MC100ELT23 MC100EL12DTR2 MC10H131FNR2 MC100H640FNR |
5V Dual Differential PECL to TTL Translator
5V ECL Low Impedance Driver
Dual Type D Master-Slave Flip-Flop
ECL/TTL Clock Driver
3.3V / 5V ECL Quad D Flip Flop with Set, Reset, and Differential Clock
3.3V / 5V ECL ÷4 Divider
Quad 2-Input NOR Gate
3.3V ECL Dual Differential Data and Clock D-Type Flip-Flop with Set and Reset
3.3V / 5V Hex Differential Line Receiver / Driver
3.3V / 5V Triple ECL Input to LVPECL/PECL Output Translator
|
ON Semiconductor
|
| MC100EP01 MC10EP445 MC10H172FNR2 MC100EL29 MC100H6 |
3.3V / 5V ECL 4-Input OR/NOR
3.3V / 5VECL 8-Bit Serial/Parallel Converter
Dual Binary 1-4-Decoder (High)
5V ECL Dual Differential Data and Clock D Flip-Flop With Set and Reset
9-Bit TTL-ECL Translator
Quad TTL-ECL Translator
Dual 2-Wide 2-3-Input OR-AND/OR-AND-Invert Gate
3.3V / 5V ECL 8-Bit Synchronous Binary Up Counter
3.3 V 1:9 Differential HSTL/PECL to HSTL Clock Driver with LVTTL Clock Select and Enable
3.3V 10-bit LVTTL/LVCMOS to LVPECL Translator
3.3V / 5V ECL Quad D Flip Flop with Set, Reset, and Differential Clock
5V ECL Voltage Controlled Oscillator
3.3V ECL D-Type Flip-Flop with Set and Reset
Binary to 1-8 Decoder (Low)
Differential -5V ECL To TTL Translator
-3.3V / -5V Triple ECL Input to PECL Output Translator
5V ECL Dual Differential 2:1 Multiplexer
Quad MSTR
5V ECL Quad 4-Input OR/NOR Gate
3.3V ECL Dual Differential Data and Clock D-Type Flip-Flop with Set and Reset
Dual 4-5-Input OR/NOR
|
ON Semiconductor
|
| MC100ES6039 MC100ES6039EGR2 MC100ES6039DW MC100ES6 |
3.3 V ECL/PECL/HSTL/LVDS /-2/4, /-4/5/6 Clock Generation Chip
3.3V ECL/PECL/HSTL/LVDS 2/4, 4/6 Clock Generation Chip 3.3 ECL / PECL HSTL / LVDS / 44 / 6时钟发生器芯
|
Freescale (Motorola)
FREESCALE[Freescale Semiconductor, Inc]
Freescale Semiconductors
飞思卡尔半导体(中国)有限公司
|
| SY10EP31VZITR SY10EP31VKI SY10EP31VKCTR SY10EP31V |
From old datasheet system
5V/3.3V, 3GHz PECL/LVPECL D FLIP-FLOP WITH SET AND RESET
|
MICREL[Micrel Semiconductor]
|
| AZ100LVEL32DG AZ10LVEL32-09 |
ECL/PECL 隆? 2 Divider
ECL/PECL ÷ 2 Divider
|
Arizona Microtek, Inc
|
| AZ100EL58 |
ECL/PECL 2:1 Multiplexer
|
Arizona Microtek
|
